DocumentCode
3556025
Title
An optimized 0.5 micron LDD transistors
Author
Rathnam, S. ; Bahramian, H. ; Laurent, D. ; Han, Yu-Pin
Author_Institution
Mostek Corporation, Carrollton, Texas
Volume
29
fYear
1983
fDate
1983
Firstpage
237
Lastpage
241
Abstract
A 0.5 micron triple diffused (LD3) NMOS transistor with a maximum operating voltage of 10 volts has been designed and fabricated. The transistor is a low doped drain type (1,3,6) with an additional boron region (halo) around the source/drain junctions. By properly tailoring this boron profile, long channel behavior can be maintained down to the sub-micron level.
Keywords
Boron; Capacitance; Circuit synthesis; DRAM chips; Doping; Implants; MOSFETs; Resists; Threshold voltage; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1983 International
Type
conf
DOI
10.1109/IEDM.1983.190485
Filename
1483610
Link To Document