Title :
A 1.3 µm N-MOS VLSI technology
Author :
Wada, Y. ; Sunami, H. ; Yamamoto, N. ; Kawamoto, Y. ; Mizutani, T. ; Yagi, K. ; Homma, Y. ; Hashimoto, N. ; Asai, Satoshi
Author_Institution :
Hitachi, Ltd., Tokyo, Japan
Abstract :
A 1.3 µm n-MOS VLSI technology developed at Hitachi Central Research Laboratory is reported. It includes fine pattern formation technology, planar device structure, low resistive gate technology and multilevel interconnection technology. The minimum dimension utilized in the test device is 1.0 µm, and the dimensional accuracy is better than 0.2 µm. Poly-Si taper etching enabled low resistive gate interconnections. The clever integration of these technologies will enable mega bit memory LSI´s.
Keywords :
Aluminum; Conductivity; Etching; Pattern formation; Planarization; Resists; Surface waves; Testing; Very large scale integration; Wiring;
Conference_Titel :
Electron Devices Meeting, 1983 International
Conference_Location :
Washington, DC, USA
DOI :
10.1109/IEDM.1983.190507
