A high performance, high density 256K DRAM utilizing IX projection lithography

The technology and design of a very dense high performance NMOS double poly 256K DRAM fabricated with full wafer 1X lithography is described. The cell storage capacitor is enhanced through the use of a self aligned N+ storage node which allows full charge capture in the cell without sacrificing packing density. The design employs a standard folded metal bit line. By combining small contacts in the cell with narrow metal bit lines, a typical bit line capacitance of 300 fF is realized. Improved performance is achieved through the use of a polycide layer made with tungsten silicide for the word lines and active devices. Both sputtered and CVD materials have been used. Typical clock delays are less than 8 ns and measured access times of 80 ns have been demonstrated. Minimum image sizes of 1.2 microns have been used on 2 mask levels.