A 1.5 micron HCMOS III technology for fast static RAMs

A 1.5 micron, 250 Å gate technology has been developed for high performance static RAMs. This new generation technology, HCMOS III, provides increased layout density and superior performance. A self-aligned well process sequence is used to form both p^-and n^-tubs. Delays in word lines and interconnections are reduced through the use of a refractory-silicide gate material. The SRAM die size is reduced by utilizing an n-channel 4-transistor memory cell with resistor loads. A graded n⁺source-drain structure is employed to reduce the hot electron trapping susceptibiity of the 1.5 micron n-channel transistor. The p⁺source-drain junctions are formed without a p⁺masking step. The power-speed limitations of the fully static design have been overcome through the use of address transition detection circuitry. This technology has been applied to a 4K×4 HCMOS SRAM as an initial test vehicle.