A review of refractory gates for MOS VLSI

As the chip size and density of integrated circuits continues to increase, the resistance of the poly-Si lines constrains the overall circuit performance. In this paper, the present status of refractory gates for enhancement or replacement of poly-Si is critically reviewed. Gate structures considered include single-level refractory metals and metal silicides, and composite poly-Si and metal structures incorporating silicldes. General issues considered include compatibility with existing MOS processes, long-term reliability and scalability to future submicron processes. Specific issues addressed include: passivation of refractory metal gates, stress-related adhesion of refractory gates, patterning of polycides, and selective formation of self-aligned silicide structures. State-of-art 256K dynamic RAM circuits implemented with and without refractory gates are reviewed. Finally, the future prospect of refractory gate technology is examined.