A fully-self-aligned joint-gate CMOS technology

A six-mask process that provides joint-gate CMOS structures with the source and drain of both transistors self-aligned to the joint-gate electrode has been developed. The features that permit the full self-alignment are an edge-defined silicon nitride "filament" (used as an oxidation mask) and overlapping polysilicon "handles" used to form the top transistor source and drain regions. The structures have been characterized as individual nMOS and pMOS transistors and are functional as joint-gate CMOS inverters.