Optimization of sub-micron p-channel FET structure

The effect of the counter-doping channel implant junction depth (Yj) and the source/drain junction depth (Xj) on the subthreshold characteristics of submicron p-channel transistors are analyzed using simulation methods. Results indicate that submicron p-channel transistors must have shallow junctions, 0.1 to 0.15um for both Xj and Yj, in order to achieve good subthreshold characteristics. Based on these results, a process was designed. Arsenic channel implant was used for controlling Yj to within 0.1um deep. Shallow p⁺source/drain junctions (0.1um) were formed with boron implant and low temperature annealing. Good subthreshold slope (80-90mV/ decade) and large punch-through voltage (5V) were measured from devices having an effective channel length (Leff) of 0.4um and a threshold voltage (Vt) of -0.6V.