DocumentCode
3556105
Title
A planar metallization process - Its application to tri-level aluminum interconnection
Author
Moriya, Takehiro ; Shima, S. ; Hazuki, Y. ; Chiba, M. ; Kashiwagi, M.
Author_Institution
Toshiba Research and Development Center, Kawasaki, Japan
fYear
1983
fDate
5-7 Dec. 1983
Firstpage
550
Lastpage
553
Abstract
A planar metallization process has been proposed, where contact windows or via holes of a high aspect ratio are refilled with tungsten by selective CVD enloloying WF6 . In tungsten selective CVD, an appropriate choice of substrate material and surface cleaning prior to tungsten deposition is a key factor to success. For selective deposition onto Al, Al surface is coated with MoSi2 thin layer, and contact resistivities of refilling tungsten with n+Si and MoSi2 coated Al are comparable to those of conventional Al metallization. Combining a interlevel insulator surface planarization process and a planar metallization process, a tri-level aluminum interconnection process of 1 micron feature size has been constructed, which has a scheme extensive to submicron feature size.
Keywords
Aluminum alloys; Argon; Conductivity; Insulation; Metallization; Planarization; Research and development; Silicon alloys; Surface cleaning; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1983 International
Conference_Location
Washington, DC, USA
Type
conf
DOI
10.1109/IEDM.1983.190565
Filename
1483690
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