Optimum design of dual control gate cell for high density EEPROMs

To realize high density EEPROMs, a new floating gate type cell with dual control gate structure has been developed and optimized. In this cell an address selection transistor is eliminated and a 1 transistor/ 1 cell structure is realized. The address selection is achieved by coincidence of two control gates which are connected to column and row decorders supplied with programming voltage. The stored charge in the floating gate suffers from disturbance by repetition of the half-selection mode operation which is defined as a state that one of the control gates is set to high and the other to low during programming. In order to improve the endurance of the cell against half-selection mode operation, a new source biasing method has been proposed, which has improved the endurance more than 3 orders of magnitude. Basic technologies for designing a 64K EEPROM chip are also described.