DocumentCode :
3556189
Title :
Twin tub III - A third generation CMOS technology
Author :
Agraz-Guerena, J. ; Ashton, R.A. ; Bertram, W.J. ; Melin, R.C. ; Sun, R.C. ; Clemens, J.T.
Author_Institution :
AT&T Bell Laboratories, Allentown, Pennsylvania
Volume :
30
fYear :
1984
fDate :
1984
Firstpage :
63
Lastpage :
66
Abstract :
A third generation Twin-Tub (1, 2) CMOS Technology was developed using 1.75 µm lines/spaces and epitaxial substrates to suppress latch-up. The 5.0 volt transistor structures use a 250 A gate oxide, polycide gates, 0.55 µm Xjand 1.3 µm nominal channel lengths, n- and p-channel thresholds of 0.7 and -1.0 volts are obtained with a blanket boron ion implant. Long channel behavior and minimal threshold changes are obtained at geometries down to 0.9 µm channel length and 1.5 µm channel width. The time for linear threshold drift of 100 mv change extrapolates to > 1E5 hours for Vd < 5.5 V. This technology has been applied to the fabrication of the WETM32100 microprocessor and memory management chips (3, 4) and SRAM devices.
Keywords :
Boron; CMOS technology; Fabrication; Geometry; Implants; Memory management; Microprocessors; Space technology; Substrates; Technology management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1984 International
Type :
conf
DOI :
10.1109/IEDM.1984.190642
Filename :
1484413
Link To Document :
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