A new device interconnect scheme for sub-micron VLSI

A new device interconnect scheme for sub-micron VLSI has been developed. In this technology N+ and P+ diffusions and N+ and P+ gates of a CMOS process can be directly connected in any combination desired without the use of contacts or aluminum. This provides much improved packing density over conventional processes. Since the source/drain (S/D) contacts can extend over the field oxide regions, minimum sized S/D diffusion areas can be used. This leads to a significant decrease in parasitic diffusion capacitances relative to other processes. Several devices can share one contact when they need to communicate, and so the total number of contacts can be greatly reduced. Since the contacts do not have to be limited to minimum dimensions a relaxation of sub-micron contact processing is achieved. In addition the use of a self-aligned silicide reduces interconnect and other device parasitic resistances. NMOS and PMOS devices have been successfully fabricated using this process.