DocumentCode
3556238
Title
An isolation-merged vertical capacitor cell for large capacity DRAM
Author
Nakajima, Shigeru ; Miura, Kenji ; Minegishi, Kazushige ; Morie, Takashi
Author_Institution
Nippon Telegraph and Telephone Public Corporation, Kanagawa, Japan
Volume
30
fYear
1984
fDate
1984
Firstpage
240
Lastpage
243
Abstract
An isolation-merged vertical capacitor (IVEC) cell is described with emphasis on its scalability, simulated device characteristics and experimentally obtained capacitor oxide breakdown voltage. The IVEC cell size will be reduced to around 5 µm2by using the 0.5 µm rule process and trench depth of 2.2 µm. Capacitor oxide breakdown voltage is nearly the same with the conventional trench capacitor.
Keywords
Capacitance; Capacitors; Electrodes; Etching; Laboratories; Random access memory; Scalability; Semiconductor films; Silicon; Telegraphy;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1984 International
Type
conf
DOI
10.1109/IEDM.1984.190691
Filename
1484462
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