Characterization and modeling of a latchup-free 1- µm CMOS technology

A 1-µm CMOS technology using thin p/p⁺epi and shallow retrograde n-well is demonstrated to be latchup free since the holding voltage for latchup is higher than the 5-V power supply. Good agreement is obtained between the experimental result and simulations using a two-dimensional finite-element numerical analysis program. The sensitivity of latchup holding voltage to epi thickness and other structural parameters are also studied in the simulation.