DocumentCode
3556333
Title
Defect generation in trench isolation
Author
Teng, Clarence W. ; Slawinski, Christopher ; Hunter, William R.
Author_Institution
Texas Instruments Incorporated, Dallas, Texas
Volume
30
fYear
1984
fDate
1984
Firstpage
586
Lastpage
589
Abstract
Defect generation in silicon during trench isolation process has been studied. Several sources of defect generation have been identified using Secco etching. These include contamination from the redeposited oxide layer during the trench etch and the stress induced at trench corners during the trench cap and field oxidation. A Sealed Sidewall Trench (SST) isolation process has been developed which results in defect-free trench isolation structures. A key addition to the refill dielectrics in SST is the incorporation of nitride layer(s) for inhibiting excessive vertical bird´s beaking.
Keywords
CMOS process; Dielectrics; Etching; Instruments; Oxidation; Plasma applications; Process design; Scalability; Silicon; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1984 International
Type
conf
DOI
10.1109/IEDM.1984.190788
Filename
1484559
Link To Document