A fully scaled submicron direct write E-beam CMOS technology for ULSI digital applications

This paper describes a 0.5µm trench isolated CMOS technology for VLSI digital applications using direct write E-beam lithography and reactive ion etching to achieve high density and performance. The principle problems facing high density, submicron CMOS technologists are minimum feature separation, latchup, and hot-electron lifetime. Our process uses 1µ wide × 5µ deep trenches to achieve minimum n/p diffusion separation and eliminate latchup. Low Doped Drain extensions were incorporated and optimized to achieve acceptable device lifetime. To further improve density and performance, self aligned, silicided poly and source/drain diffusion are used to lower series resistance and provide short range first level interconnect.