DocumentCode
3556350
Title
A highly reliable N-MOS process for one megabit dynamic random access memory
Author
Matsukawa, T. ; Inuishi, M. ; Mitsuhashi, J. ; Hirayama, M. ; Tsukamoto, K. ; Uoya, S. ; Yoshihara, T. ; Nakata, H.
Author_Institution
Mitsubishi Electric Corporation, Hyogo, JAPAN
Volume
30
fYear
1984
fDate
1984
Firstpage
647
Lastpage
650
Abstract
An n-channel MOS process has been developed to yield reliable one megabit dynamic RAMs. Main features of the process are as follows; * Adoption of epitaxial-growth wafer * Bird´s beak-reduced LOCOS isolation * Highly reliable memory cell capacitor with 10nm SiO2 * Low resistivity TiSi2 polycide gate electrode * Al-Si-Ti interconnection with low temperature planarization of the underlying layer * 1.2µm pattern formation by a 5:1 step and repeat aligner followed by the reactive ion etching A highly reliable 1M×1 dynamic MOS memory was successfully fabricated using these processes.
Keywords
DRAM chips; Epitaxial growth; Etching; Fabrication; Glass; Lithography; MOS capacitors; Pattern formation; Planarization; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1984 International
Type
conf
DOI
10.1109/IEDM.1984.190805
Filename
1484576
Link To Document