An 80 ps ECL circuit with high current density transistor

Optimization of device parameters of a high speed bipolar transistor has been made to realize an extremely high speed ECL circuit. Using the transistor, an ECL circuit with a gate delay time of 80 ps has been obtained, where the current density is 0.35 mA/µm². The transistor is of a polysilicon-self-aligned, 1.25 µm lithography technology and shallow emitter and base junctions, prepared in a one micron thin epi-layer. The cut-off frequency of the transistor is 9 GHz. Gate delay time vs. current density dependences for several couples of emitter dimensions, base and collector carrier concentration variations were studied to find out the optimal device parameters. It has been shown that the collector carrier concentration is the most critical in reducing.