SOI-CMOS 4K SRAM with high dose oxygen implanted substrate

This paper reports on the fabrication of a SOI-CMOS 4K SRAM using the implanted buried oxide SOI technology with a minimum feature size of 2.5 µm. The 4K×1 CMOS SRAM, using a 6T cell which contained n-channel loads and p-channel driver and pass transistors, exhibited a power dissipation of 85 mW at 5V Vdd and an address access time of 55 ns which agreed with the SPICE simulations. Electrical parameters of the buried oxide SOI devices were compared to those of the bulk CMOS devices. Except for an approximately 10% degradation of the carrier mobility and the "kink" effect due to the floating body node, the buried oxide SOI devices were indistinguishable from the bulk devices. The uniformity of the buried oxide SOI device parameters is emphasized.