2 Micron merged bipolar-CMOS technology

A 2 µm process, merging the major technologies required to fabricate VLSI MOS and bipolar transistors on the same integrated circuit, is described. Two mask steps are added to a two-layer metal N-well silicided CMOS process to fabricate the walled-polysilicon emitter NPN transistors. The non-epitaxial process was used to establish the current drive advantage gained by integrating NPN transistors with CMOS. By adding a 1 µm epitaxial layer and adopting a retrograde P-well, latchup is eliminated and VLSI bipolar performance becomes feasible.