DocumentCode :
3556393
Title :
Fabrication of high speed 1 micron FIPOS/CMOS
Author :
Anzai, K. ; Otoi, F. ; Ohnishi, M. ; Kitabayashi, H.
Author_Institution :
Oki Electric Industry Co., Ltd., Tokyo, Japan
Volume :
30
fYear :
1984
fDate :
1984
Firstpage :
796
Lastpage :
799
Abstract :
High Speed 1 micron FIPOS/CMOS devices, 100 stages inverter chains and 1/8 dynamic frequency divider, have been developed and successfully fabricated. The fabrication process and the speed performance are discussed in this report. A high pressure oxidation is advantageous for reducing the wafer warpage in FIPOS process and applicable to the fabrication process. DDD structure or SPD structure for NMOS, and the shallow junction formed by BF2Implantation for PMOS, are applied to fabrication of the 1 micron FIPOS/CMOS. The devices have a high speed performance, 60psec stage delay at Vdd=5 V and maximum operating frequency Fmax=1 GHz.
Keywords :
CMOS logic circuits; CMOS process; CMOS technology; Fabrication; Geometry; Leakage current; Logic arrays; MOS devices; Silicon; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1984 International
Type :
conf
DOI :
10.1109/IEDM.1984.190847
Filename :
1484618
Link To Document :
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