• DocumentCode
    3556452
  • Title

    A high density GaAs static RAM process using MASFET

  • Author

    Kato, Naoki ; Hirayama, Masahiro ; Asai, Kazuyoshi ; Matsuoka, Yutaka ; Yamasaki, Kazuhiko ; Ogino, Tadashi

  • Author_Institution
    NTT Atsugi Electrical Communication Laboratories, Kanagawa, Japan
  • Volume
    31
  • fYear
    1985
  • fDate
    1985
  • Firstpage
    90
  • Lastpage
    93
  • Abstract
    A newly-developed GaAs static RAM process is described. A large transconductance (gm) of 260 mS/mm has been obtained for enhancement-mode FETs. The large transconductance is accomplished with both buried p-layer SAINT (BP-SAINT) and shallow 30 keV n-layer ion implantation applied to Metallic Amorphous Silicon gate (MAS) FET. A novel static RAM cell layout drastically reduces its cell area to 455 µm2. To realize such a compact cell, tri-level interconnections and electron beam delineated 0.8 µm × 1.3 µm via holes directly on gates and ohmic metals have been developed.
  • Keywords
    Amorphous silicon; FETs; Gallium arsenide; Integrated circuit interconnections; Ion implantation; Laboratories; Read-write memory; Scattering; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1985 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1985.190899
  • Filename
    1485449
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3556452