Fabrication and characterization of sub-micron thin gate oxide p-channel transistors with p+ polysilicon gates

Submicron p-channel transistors have been fabricated using thin (150 A) gate oxide and p⁺polysilicon gates. Quite favorable device characteristics have been achieved for L(eff) as low as 0.4 microns. GEMINI simulations have been performed which demonstrate the advantages of p⁺poly in reducing short channel effects and punchthrough problems. Experimental results from three separate device lots show good subthreshold slope and low leakage current, even for low threshold voltages. Vt vs. L(eff) shows much less threshold drop than is seen using n+ poly. Device characteristics are robust with respect to processing variations. CV data shows little if any boron penetration through the 150 A gate oxide.