A new high density full CMOS SRAM cell using polysilicon interconnection structure

A new polysilicon interconnected full CMOS SRAM cell, lying only three metal lines and performing reduced latchup susceptibility and small cell area, is described. In this memory cell, PMOS and NMOS drain terminals are interconnected through double Polysilicon layer, and metal lines are used as two bit lines and power supply line, which enables substrate to be strapped to supply voltage level without any additional substrate bias area in memory cell array. Applying this new technique to a memory cell using 1.2µm ground rule, the cell size, 9.9 × 14.3µm², is shrunk about seventy five percent that of the conventional structure full CMOS cell and is practically expected to be realized 256K bit full CMOS SRAM. In future era of a mega bit or more high density SRAM, a full CMOS cell with multi-level connection layers will overcome its low packing density and surely become the alternative to a high resistive load NMOS cell.