Scaling limitations of submicron local oxidation technology

Scaling limitations of LOCOS technology into the submicron regime is explored. Device isolation structures with submicron lines and spaces are fabricated using electron beam lithography. Various LOCOS isolation technologies such as SWAMI, SILO and a new SILO/SWAMI technology are investigated for their scalability to isolation spacing width below one micron based on the requirements of VLSI CMOS technology. It is found that there are two major limitations to the scaling of any LOCOS technology. The first one is the thinning of field oxide with narrower isolation spacing. The second one is the need for a gentle oxidation profile inside silicon for defect free isolation.