• DocumentCode
    3556543
  • Title

    Lightly impurity doped (LD) Mo silicide gate technology

  • Author

    Kakumu, Masakazu ; Matsunaga, Jun´Ichi

  • Author_Institution
    Toshiba Corporation, Kawasaki, Japan
  • Volume
    31
  • fYear
    1985
  • fDate
    1985
  • Firstpage
    415
  • Lastpage
    418
  • Abstract
    Lightly impurity Doped (LD) Mo silicide gate technology has been developed. LD Mo silicide gate technology provides a non-degenerated gate material, where the temperature dependence of the Fermi level in the channel region can be cancelled. This technology has been applied to CMOS devices to demonstrate high speed operation at low temperatures.
  • Keywords
    CMOS technology; Impurities; Integrated circuit interconnections; MOS devices; MOSFET circuits; Semiconductor materials; Silicides; Temperature dependence; Temperature distribution; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1985 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1985.190989
  • Filename
    1485539
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3556543