• DocumentCode
    3556606
  • Title

    A high performance memory cell technology for mega bit EPROMS

  • Author

    Komori, K. ; Kuroda, K. ; Meguro, S. ; Nagasawa, K. ; Fukuda, M. ; Uchibori, K. ; Hagiwara, T.

  • Author_Institution
    Hitachi Ltd.
  • Volume
    31
  • fYear
    1985
  • fDate
    1985
  • Firstpage
    627
  • Lastpage
    630
  • Abstract
    A high performance memory cell technology for mega bit EPROMs has been developed using 1.3 µm process. Deeply Doped Channel ( DDC ) and Double Step Drain ( DSD ) structures incorporated into the scaled memory cell improve programming speeds by more than one order of magnitude with maintaining high breakdown voltages, small parasitic effects,and soft-write immunity. This technology has been successfully applied to one mega bit CMOS EPROMs with a cell size of 19.27 µm2and realized programming time less than 10 µs for a programming voltage of 12.5 V.
  • Keywords
    Boron; CMOS technology; Capacitance; EPROM; Implants; Laboratories; Nonvolatile memory; Testing; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1985 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1985.191051
  • Filename
    1485601
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3556606