A new EPROM cell with a side-wall floating gate for high-density and high-performance device

A new EPROM cell has been proposed to realize high-density EPROM. The new cell has a similiar structure to the usual n-channel MOSFET, except for a side-wall floating gate formed on one side of a control gate. which requires only about 60% area of conventional stacked gate type cell, and enables higher density with reduced programming voltage. The new cell exchanges the roles of source and drain in the program mode and the read-out mode. The program time for Lmask=1.0µm sample is found 25msec for Vgp=Vdp=7V, 1.2msec for Vgp=Vdp=8V, and 80µsec for Vgp=Vdp=9V, being evaluated with respect to the current flows through the cell at Vgr=Vdr=3V in the read-out mode. The apparent programming characteristics depend on the bias condition in the read-out mode. Since the floating gate exists only on the source side in the read-out mode, very good tolerance to unexpected programming is achieved.