A high-speed submicrometer CMOS/SOS process in spear material

A CMOS/SOS process technology is described that has been designed for gate lengths in the 0.5-0.7 µm range. The starting material was 0.3-µm-thick SOS, recrystallized using the SPEAR process to remove defects from the as-grown material. Thin gate oxides (12 nm) and rapid thermal annealing were employed to minimize short-channel effects. Threshold voltages, punchthrough voltages, and leakage currents were found to be independent of gate length for n- and p-transistors down to 0.6 µm. Inverter speeds of 52 psec at 5 V were measured for L = 0.5 µm. A 750-transistor 0.6-µm circuit consisting of a divide-by-256 frequency divider driven by a 61-stage 2-NAND ring oscillator was also fabricated.