Technology for the fabrication of A 1 MB CMOS DRAM

We describe the cell structure and fabrication methods employed for a practical 1 MB CMOS DRAM. This process combines concentrated efforts in the cell array with a core technology of 1.25 uM Twin-Tub CMOS to provide a chip that is manufactured with standard DSW photolithography in 11 reticle levels. Nitride/ oxide dual dielectric is used as the storage gate for low defect density and resistance to time-dependent dielectric breakdown. Circuit immunity against hot carrier effects is provided through the use of double diffused drains coupled with a novel circuit technique that limits drain fields to safe values.