• DocumentCode
    3556631
  • Title

    A three-dimensional DRAM cell of stacked switching-transistor in SOI (SSS)

  • Author

    Ohkura, M. ; Kusukawa, K. ; Sunami, H. ; Hayashida, T. ; Tokuyama, T.

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • Volume
    31
  • fYear
    1985
  • fDate
    1985
  • Firstpage
    718
  • Lastpage
    721
  • Abstract
    A new three-dimensional one-transistor dynamic RAM cell is presented. It has a trench capacitor fabricated in the Si substrate. In addition, there is a switching transistor fabricated in a laser-induced SOI layer formed on top of the capacitor area. The cell´s advantages are a high capacitor capture ratio (capacitor area/cell area) and the capability of possessing high capacitance even when the cell size is reduced to less than 5µm2.
  • Keywords
    Capacitance; Capacitors; DRAM chips; Epitaxial growth; Fabrication; Impurities; Insulation; Laboratories; Random access memory; Silicon on insulator technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1985 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1985.191076
  • Filename
    1485626
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3556631