Integrable high voltage CMOS: Devices, process application

A high voltage (HV) CMOS process has been developed. This process allows one to easily create junction isolated HVCMOS structures on the same chip with low voltage (LV) CMOS structures. The HV structures, which are realized in a 3.5µm CMOS technology were designed for and achieved 100V operation. The process allows for the isolation of LV and HV devices and circuits. The technology is suited for applications which require the marriage of LV analog and digital signal processing and control circuitry with HV output buffers and drivers.