0.5 µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation

A high-performance 0.5µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation is described. It features dual polysilicon work functions (n⁺-poly for n-channel and p⁺-poly for p-channel transistors), 12.5nm gate oxide, deep threshold-adjust ion implantation for the n-channel device, shallow arsenic and boron source/drain diffusions, and thin self-aligned titanium silicide. The power supply voltage is chosen to be 2.5V based on performance, hot-carrier effects, and power dissipation considerations. The dual-work-function polysilicon gates are doped by the source/drain ion implantations. The sheet resistance of self-aligned silicide improves from roughly 4ω/sq at 300K to about 1ω/sq at 77K. Excellent device characteristics and functional ring oscillator circuits were obtained at 77K with roughly a 2X improvement in both the speed and the power-delay product over the room-temperature technology operated at 300K.