Title :
1.0 µm CMOS process for highly stable tera-ohm polysilicon load 1Mb SRAM
Author :
Hoshi, N. ; Kayama, S. ; Nishihara, T. ; Aoyama, J. ; Komatsu, T. ; Shimada, T.
Author_Institution :
Sony Corporation, Atsugi, Japan
Abstract :
An improved LOCOS and highly stable tera-ohm polysilicon load have been incorporated to fabricate 1Mb SRAM using 1.0 µm CMOS process. Main features of the process are as follows: *Double-polysilicon, double-metal process *Adoption of retrograde P-well *Low temperature planarization by using AsSG reflow and SOG coating *Low temperature processing (950°C max). With these technologies and processes, a 1Mb CMOS SRAM was successfully fabricated with a typical standby current of 5 µA and 6.4 ×11.6 µm2cell size.
Keywords :
CMOS process; CMOS technology; Coatings; Leakage current; Planarization; Plasma applications; Plasma materials processing; Plasma temperature; Random access memory; Silicon;
Conference_Titel :
Electron Devices Meeting, 1986 International
Conference_Location :
Los Angeles, CA, USA
DOI :
10.1109/IEDM.1986.191175
