Title :
Advanced BiCMOS technology for high speed VLSI
Author :
Ikeda, T. ; Nagano, T. ; Momma, N. ; Miyata, Kenji ; Higuchi, H. ; Odaka, M. ; Ogiue, K.
Author_Institution :
Device Development Center, Tokyo, Japan
Abstract :
This paper describes the high performance BiCMOS (Hi-BiCMOS) device technology and discusses the scalability to sub-micron. As the device structure is scaled down from 2 µm to 1.3 µm, BiCMOS circuit performance is improved by the factor of the scaling. By further scale down to 0.8 µm, a 0.27 ns gate delay in BiCMOS gate and 5.5 ns access time of 64kbit BiCNOS ECL RAN are expected.
Keywords :
BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Delay effects; Fabrication; Impurities; MOS devices; Scalability; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1986 International
DOI :
10.1109/IEDM.1986.191205
