DocumentCode
3556778
Title
A 3GHz lateral PNP transistor
Author
Nakazato, Kazuo ; Nakamura, Tohru ; Kato, Masataka
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
32
fYear
1986
fDate
1986
Firstpage
416
Lastpage
419
Abstract
Using SICOS (sidewall contact structure) technology, a high speed lateral pnp transistor was fabricated and high cutoff frequency of 3GHz was obtained. This new lateral pnp transistor is comapatible with the vertical npn transistors without any additional fabrication steps. ECL ring oscillator constructed by SICOS lateral pnp transistors exhibited 216 psec/gate delay time. This delay time is comparable to the speed of modern ECL gates using isoplanar vertical npn transistors. High performace pnp transistors will increase the applicability of bipolar VLSIs.
Keywords
Bipolar transistor circuits; Charge carrier processes; Cutoff frequency; Delay effects; Electrodes; Equations; Fabrication; Parasitic capacitance; Silicon compounds; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1986 International
Type
conf
DOI
10.1109/IEDM.1986.191207
Filename
1486465
Link To Document