Submicron epitaxial layer and RTA technology for extremely high speed bipolar transistors

This paper will describe an extremely high speed bipolar transistor with which we achieved an ECL gate delay of as fast as 52ps. To realize the high speed transistor, a submicron epitaxial layer, 1µm ruled polysilicon self-aligned technology and rapid thermal annealing (RTA) technology were utilized. Using the scaled down transistor, optimization of RTA conditions and epitaxial layer thickness was investigated. The highest ECL gate speed was obtained under optimized conditions of 0.7µm thick epitaxial layer and RTA at 1050°C-10sec. The current density of the minimum gate delay point was 0.67mA/µm². The cut-off frequency of the transistor was 13GHz.