Title :
63 ps ECL circuits using advanced SICOS technology
Author :
Nakamura, Tohru ; Ikeda, Kiyoji ; Nakazato, Kazuo ; Washio, Katsuyoshi ; Namba, Mitsuo ; Hayashida, Tetsuya
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A high speed silicon bipolar transistor structure and very high speed ECL circuits are demonstrated. The circuits were fabricated with an advanced SICOS technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI=1 and 79 ps/G at FI=3 were obtained with advanced SICOS technology.
Keywords :
Bipolar transistors; Circuit simulation; Cutoff frequency; Delay; Electrodes; Fabrication; Isolation technology; Laboratories; Parasitic capacitance; Silicon;
Conference_Titel :
Electron Devices Meeting, 1986 International
DOI :
10.1109/IEDM.1986.191223
