Modeling of hot electron effects on the device parameters for circuit simulation

A practical and realistic assessment of hot electron degradation effects on circuit performances was examined. Device parameters were monitored after each stress operation for NMOS FET´s with several different channel lengths. Quantitative descriptions of all the critical parameters as a function of stress time and stress substrate current were established. Device simulations for the transistors with negative fixed interface charges localized near the drain have confirmed the hot-carrier degradation results observed experimentally. Circuit simulation results for a ring oscillator and an inverter chain circuits using the parameters corresponding to the conventional criteria for determining device lifetime and that of a more realistic approach were compared.