• DocumentCode
    3556898
  • Title

    Bipolar CMOS merged structure for high speed M bit DRAM

  • Author

    Kobayashi, Y. ; Oohayashi, M. ; Asayama, K. ; Ikeda, T. ; Hori, R. ; Itoh, K.

  • Author_Institution
    Hitachi Ltd., Hitachi, Ibaraki, Japan
  • Volume
    32
  • fYear
    1986
  • fDate
    1986
  • Firstpage
    802
  • Lastpage
    804
  • Keywords
    Bipolar transistors; CMOS process; CMOS technology; Capacitance; Driver circuits; Error analysis; Fabrication; Laboratories; MOSFET circuits; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1986 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1986.191317
  • Filename
    1486575
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3556898