A testable CMOS signal processor for fast Fourier transforms

Author

Ramakrishna, N.A. ; Boyoumi, M.A.

Author_Institution

Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA

fYear

1988

fDate

7-9 Jun 1988

Firstpage

73

Abstract

The authors present the architecture of a fast Fourier transform processor which has high performance characteristics and an embedded test structure that allows the processor to test itself during normal operation. The properties of separable residue codes have been used for error detection in the arithmetic unit of the processor. Offline error detection which tests for the classic stuck at faults is based on the properties of the dynamic CMOS logic design used. The testing circuitry used in the architecture accounts for only a 20% area overhead and no time ahead, an important saving in a signal-processing environment

Keywords

CMOS integrated circuits; computer architecture; digital signal processing chips; fast Fourier transforms; integrated circuit testing; logic testing; CMOS signal processor; DFT; FFT; area overhead; arithmetic unit; design for testability; dynamic CMOS logic design; embedded test structure; error detection; fast Fourier transform processor; fast Fourier transforms; separable residue codes; signal-processing environment; test itself during normal operation; testing circuitry; Arithmetic; CMOS process; Circuit faults; Circuit testing; Electrical fault detection; Fast Fourier transforms; Fault detection; Logic design; Logic testing; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo

Type

conf

DOI

10.1109/ISCAS.1988.14871

Filename

14871