DocumentCode
3556972
Title
A high speed super self-aligned bipolar-CMOS technology
Author
Chiu, Tzu-Yin ; Chin, Gen M. ; Lau, Maureen Y. ; Hanson, Ronald C. ; Morris, Mark D. ; Lee, Kwing F. ; Voshchenkov, Alexander M. ; Swartz, Robert G. ; Archer, Vance D. ; Finegan, Sean N.
Author_Institution
AT&T Bell Laboratories, Holmdel, NJ
Volume
33
fYear
1987
fDate
1987
Firstpage
24
Lastpage
27
Abstract
An ideal device structure for integrating bipolar and CMOS is reported in this paper. Both the vertical npn and MOS devices have new non-overlapping super self-aligned structures. With a single 5V supply, averaged per stage delay of 82ps and 125ps have been measured for 0.6µm and 0.85µm (Leff ) CMOS ring oscillators. Bipolar transistors have also been fabricated with a nominal current gain of 100.
Keywords
BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Delay; Implants; MOS devices; Merging; Ring oscillators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1987 International
Type
conf
DOI
10.1109/IEDM.1987.191338
Filename
1487296
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