• DocumentCode
    3556973
  • Title

    0.8 µm Bi-CMOS technology with high fTion-implanted emitter bipolar transistor

  • Author

    Iwai, Hisato ; Sasaki, G. ; Unno, Y. ; Niitsu, Y. ; Norishima, M. ; Sugimoto, Yoshiki ; Kanzaki, K.

  • Author_Institution
    Toshiba Corporation, Kawasaki, Japan
  • fYear
    1987
  • fDate
    6-9 Dec. 1987
  • Firstpage
    28
  • Lastpage
    31
  • Abstract
    A submicron Bi-CMOS technology with direct ion-implanted emitter bipolar transistor has been developed. The process base is the 0.8µm CMOS process. For the bipolar transistor, an ion-implanted emitter structure was chosen to minimize the production cost. By optimizing the bipolar transistor, a sufficiently high performance for Bi-CMOS gates has been obtained. The direct ion-implanted emitter Bi-CMOS process would be popular to attain high speed submicron VLSIs, due to good mass-productivity and sufficiently high performance.
  • Keywords
    Annealing; Bipolar transistors; Boron; CMOS process; Capacitance; Contact resistance; Ion implantation; Logic devices; SPICE; Surface resistance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1987 International
  • Conference_Location
    Washington, DC, USA
  • Type

    conf

  • DOI
    10.1109/IEDM.1987.191339
  • Filename
    1487297
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3556973