Title :
Hot carrier aging in two level metal processing
Author :
Chen, M.-L. ; Leung, C.-W. ; Cochran, W.T. ; Jain, S. ; Hey, H.P.W. ; Chew, H. ; Dziuba, C.
Author_Institution :
AT&T Bell Laboratories, Allentown, PA
Abstract :
This paper describes device degradation induced during processing steps often used in submicron CMOS multi-level metal technologies. D.C. stressed device aging is used to characterize process induced device degradation. The aging characteristics are degraded with certain types of second layer metal processing. Once the devices are capped with conventional SIN, there is no significant difference in the aging characteristics.
Keywords :
Aging; CMOS process; CMOS technology; Degradation; Electron traps; Etching; Hot carriers; Silicon compounds; Stress; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1987 International
DOI :
10.1109/IEDM.1987.191346
