DocumentCode
3557028
Title
Submicron wiring technology with tungsten and planarization
Author
Kaanta, Carter ; Cote, William ; Cronin, John ; Holland, Karey ; Lee, Pei-Ing ; Wright, Terry
Author_Institution
IBM General Technology Division, Essex Junction, Vermont
Volume
33
fYear
1987
fDate
1987
Firstpage
209
Lastpage
212
Abstract
A submicron wiring technology has been designed, built, and proven reliable. This fully integrated technology features CVD-tungsten (W) and planarization. Vertical W studs maximize density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability.
Keywords
Capacitance; Circuit optimization; Insulation; Integrated circuit reliability; Metal-insulator structures; Planarization; Plasma temperature; Space technology; Tungsten; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1987 International
Type
conf
DOI
10.1109/IEDM.1987.191389
Filename
1487347
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