DocumentCode :
3557072
Title :
Self-aligned contact schemes for source-drains in submicron devices
Author :
Lynch, W.T.
Author_Institution :
AT&T Bell Laboratories, Murray Hill, New Jersey
Volume :
33
fYear :
1987
fDate :
1987
Firstpage :
354
Lastpage :
357
Abstract :
This paper reviews the basic limitations in source-drain parasitics and source-drain contacts as devices are scaled to the submicron regime. The major portion of the paper reviews the various proposals to provide local interconnect layers which interface with the source-drain and from which all contact windows to metal-1 are made over field oxide. Among the promising approaches are HPSAC, TiN local interconnect, BOMOS and UPMOS. Significant improvements in parasitic reduction, layout density, and reliability can be achieved.
Keywords :
Contact resistance; Doping profiles; MOSFET circuits; Parasitic capacitance; Plugs; Proposals; Silicides; Silicon devices; Surface resistance; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1987 International
Type :
conf
DOI :
10.1109/IEDM.1987.191430
Filename :
1487388
Link To Document :
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