A super self-aligned source/drain MOSFET

A novel MOSFET structure is presented in which the source/drain area is minimized by self-aligning to the gate polysilicon. This is achieved by forming a nitride spacer followed by a second field oxidation after gate delineation. A selective silicon growth technique is used to extend the source/drain over the second field oxide for easy contacting. A fully self-aligned contact scheme is employed to conserve overall device area. Besides saving device area and minimizing parasitic capacitance, experimental results at one-micron geometry indicate that other device characteristics are similar to that of the conventional LDD-MOSFET. This device is expected to be scalable well into the submicron regime.