Title :
An 0.8 µm CMOS technology for high performance logic applications
Author :
Chapman, R.A. ; Haken, R.A. ; Bell, D.A. ; Wei, C.C. ; Havemann, R.H. ; Tang, T.E. ; Holloway, T.C. ; Gale, R.J.
Author_Institution :
Texas Instruments Incorporated, Dallas, Texas
Abstract :
This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.
Keywords :
Boron; CMOS logic circuits; CMOS technology; Implants; Leakage current; Logic circuits; MOS devices; Oxidation; Testing; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1987 International
Conference_Location :
Washington, DC, USA
DOI :
10.1109/IEDM.1987.191432
