0.25 µm CMOS technology using P+polysilicon gate PMOSFET

A 0.25 µm-channel CMOS Technology, in addition to a latchup-free 0.25 µm isolation technique, has been developed, using p⁺poly-Si gate pMOSFET. The p⁺poly-Si gate pMOSFET with shallow source/drain junctions, which has symmetric impurity profile to an n⁺poly-Si gate nMOSFET, is optimized by using a low energy BF2⁺implant, combined with a low temperature furnace annealing, followed by a rapid thermal annealing. A short channel effect for both nMOSFET and pMOSFET is reduced, by achieving the shallow junctions and thin gate oxide. Power supply voltage must be reduced to 3V or less in order to maintain n-channel device reliability.