Title :
A flash-erase EEPROM cell with an asymmetric source and drain structure
Author :
Kume, H. ; Yamamoto, H. ; Adachi, T. ; Hagiwara, T. ; Komori, K. ; Nishimoto, T. ; Koike, A. ; Meguro, S. ; Hayashida, T. ; Tsukada, T.
Author_Institution :
Hitachi Ltd., Kokubunji, Japan
Abstract :
A flash-erase EEPROM cell which consists of a single floating gate transistor is described. The cell is based on self-aligned double polysilicon stacked gate structure without a select transistor. It is programmed and erased by hot electrons at the drain edge similar to a UV-EPROM, and by Fowler-Nordheim tunneling of electrons from the floating gate to the source, respectively. An asymmetry in source and drain regions is introduced to enable fast program/erase operation. In addition, an n+concentration in the source region is optimized to achieve reproducible erasure, which is indispensable to avoid over-erasing problem. The optimized cell enables an erasing time of less than one millisecond with 12. 5 V on the source, and a scatter of erased Vth is almost negligible. Endurance and data retention characteristics is also adequate for implementation in memory chips. The small cell area of 9.3µm2is accomplished in a 0.8µm technology.
Keywords :
Costs; Doping; EPROM; Electrons; Laboratories; Leakage current; Nonvolatile memory; Scalability; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 1987 International
DOI :
10.1109/IEDM.1987.191487