A practical trench isolation technology with a novel planarization process

We develop a new vertical-trench isolation method that utilizes a thin SiO2film in-between double photoresists for uniform top-resist coating and for an etch-back barrier, a poly-silicon film above active regions for an etch-back buffer and large tilt-angle boron ion implantations into the trench-sidewalls for narrow channel effect control. The Planarization with the Resist / Oxide / Resist and the Poly _Silicon (PRORPS) can isolate the whole surface of a 6 inch-diameter wafer very uniformly with a large process margin. The standard deviation of the threshold voltage of a n-channel MOS-FET (W/L= 10µm/0.8µm) over the whole wafer is 0.38 % at about 0.6 V threshold voltage. The narrow-channel-effect is controlled for FET´s down to 0.5 µm channel width. The method is applied to the megabit SCC (Surrounded Capacitor Cell) DRAM developed here and the cells and the peripheral-circuits are isolated at the same time successfully.